HiSilicon3531dv200Core Board

Project: Board Introduction | page_id: 884

1. Core Board Introduction

Board size: 124*94mm

Core Board Pin Definition

2. CPU Specifications

Description
Hi3531DV200 is a new-generation professional SoC chip developed for multi-channel HD/UHD (1080p/4M/5M/4K) DVR product applications. Hi3531DV200 integrates an ARM A53 quad-core processor and a powerful neural network inference engine, supporting a variety of intelligent algorithm applications.
Features

Processor Core
• ARM Cortex A53 quad core @1.15GHz
− 32KB L1 I-Cache, 32KB L1 D-Cache
− 512KB L2 Cache
− Supports NEON/FPU

Multi-Protocol Video Encoding/Decoding
• H.265 Main Profile, Level 5.0 encoding
• H.265 Main Profile, Level 5.1 decoding
• H.264 Baseline/Main/High Profile, Level 5.1 encoding
• H.264 Baseline/Main/High Profile, Level 5.2 decoding
• MJPEG/JPEG Baseline encoding/decoding

Video Encoding/Decoding Processing
• H.265/H.264&JPEG multi-stream codec performance:
− 8x1080p@30fps H.265/H.264 encoding
+ 8xD1@30fps H.265/H.264 encoding
+ 8x1080p@30fps H.265/H.264 decoding
+ 8x1080p@2fps JPEG encoding
− 16x1080p@15fps H.265/H.264 encoding
+ 16xD1@30fps H.265/H.264 encoding
+ 16x1080p@15fps H.265/H.264 decoding
+ 16x1080p@2fps JPEG encoding
− 16x4M@7.5fps H.265/H.264 encoding
+ 16xD1@30fps H.265/H.264 encoding
+ 16x4M@7.5fps H.265/H.264 decoding
+ 16x4M@1fps JPEG encoding
• Supports seven rate control modes: CBR/VBR/AVBR/CVBR/FIXQP/QPMAP/QVBR
• Maximum output bitrate 20Mbps
• Supports region of interest (ROI) encoding
• Supports color-to-gray encoding

SVP Smart Vision Processing
• Neural network inference engine (NNIE)
− Supports various neural networks
− 1.2Tops computing performance
− Supports a complete API and toolchain
− Supports face detection/recognition, object detection/tracking and other applications
• Intelligent vision engine (IVE)
− Supports object tracking
• Matrix arithmetic unit (MAU)
− Supports single-precision/half-precision floating point
− Supports feature vector comparison

Video and Graphics Processing
• Supports de-interlace, sharpening, 3D denoise, dynamic contrast enhancement, mosaic processing and other pre-/post-processing
• Supports anti-flicker processing for video and graphics output
• Supports video 1/15～16x scaling
• Supports graphics 1/2～2x scaling
• Supports 4 occlusion regions
• Supports 8-region OSD overlay

Video Interfaces
• Video input interface
− Supports 8 MIPI D-PHY interfaces and 1 BT.1120 video cascade interface
− Each MIPI interface supports:
• 4 lanes, max rate 1.5Gbps
• Supports single-channel input or 2-channel/4-channel multiplexed input
• Can be multiplexed as one 8bit BT.656 interface
− Every 2 BT.656 interfaces can form one 16bit BT.1120 interface
− Both BT.656 and BT.1120 support 148.5MHz dual-edge sampling
− Supports 33 video input channels (including 1 video cascade channel)
− Supports 16-channel online video scaling
− Supports simultaneous output of the original image and the scaled image
− MIPI interface max input performance:
• 8-channel 4K@30fps or 16-channel 4K@15fps
• 16-channel 4M@30fps or 16-channel 5M@20fps
• 32-channel 1080p@30fps
− Max output performance: 16-channel 1080p@30fps (or 4M/5M/4K images of the same data volume) + 1-channel 4K@30fps (cascaded input image)
• Video output interface
− Supports one HDMI 2.0 HD output interface, max output 3840x2160@60fps
− Supports one VGA HD output interface, max output 2560x1600@60fps
− Supports one BT.1120 HD output interface, max output 3840x2160@30fps (dual-edge sampling)
− Supports one CVBS SD output interface, supporting PAL/NTSC output
− Supports two independent HD output channels (DHD0, DHD1)
• Supports non-synchronous display on any two HD interfaces
• DHD0 supports 64-window split
• DHD1 supports 64-window split
− Supports one independent SD output channel (DSD0)
− Supports one PIP layer, which can be overlaid on DHD0 or DHD1
− Supports 2 GUI graphics layers, supporting ARGB1555, ARGB4444 or ARGB8888 format, for DHD0 and DHD1 respectively
− Supports one special graphics layer, supporting CLUT2/CLUT4, which can be bound to DHD0, DHD1 or DSD0
− Supports one hardware cursor layer, format configurable as ARGB1555, ARGB4444 or ARGB8888, max resolution 256x256

Audio Interfaces
• 3 unidirectional I2S/PCM interfaces
− 2 inputs, supporting 20-channel composite input
− 1 output, supporting dual-channel output

Network Interfaces
• 2 Gigabit Ethernet interfaces
− Supports RGMII and RMII interface modes
− Supports 10/100Mbit/s half-duplex or full-duplex
− Supports 1000Mbit/s full-duplex
− Supports TSO to reduce CPU overhead

Security Engine
• Supports AES 128/192/256 bit encryption/decryption algorithms
• Supports RSA 2048/4096 bit encryption/decryption algorithms
• Supports SHA256/HMAC_SHA1/
• HMAC_SHA224/HMAC_SHA256
• Supports OTP, providing 28Kbit user-programmable space
• Supports a hardware true random number generator
• Supports secure boot
• Supports secure memory isolation

Peripheral Interfaces
• 4 SATA3.0/PCIe 2.0 multiplexed interfaces
− Can be configured as 4SATA, 2SATA+1PCIe x2, 2SATA+2PCIe x1, 2PCIe x2 and other combinations
− When used as a PCIe 2.0 interface, supports RC and EP modes
− When used as a SATA 3.0 interface, supports eSATA and PM
• 1 USB 3.0 Host interface
• 2 USB 2.0 Host interfaces
• 5 UART interfaces, 2 of which support 4 wires
• 1 SPI interface, supporting 4 chip selects
• Supports 1 IR interface
• Supports 2 I2C interfaces
• Supports multiple GPIO interfaces

Memory Interfaces
• 2 32bit DDR4/DDR3 interfaces
− Supports dual channel
− DDR4 max clock frequency 1200MHz
− DDR3 max clock frequency 1066MHz
− Max capacity 8GB
• SD/MMC interface
− Supports eMMC4.5/eMMC5.0/eMMC5.1
− Supports HS400 (150MHz dual-edge)
− Supports SDIO 3.0 (not SD card)
• SPI NOR/NAND Flash interface
− Supports 2 chip selects, each can connect a different type of Flash
− For SPI NOR Flash
• Supports 1/2/4-wire modes
• Supports 3Byte and 4Byte address modes
• Max supported capacity: 256MB
− For SPI NAND Flash
• Supports SLC Flash
• Supports 2KB/4KB page size
• Supports 8/24bit ECC (ECC per 1KB)
• Max supported capacity: 2GB

Independently Powered RTC
The RTC can be independently powered by a battery

Multiple Configurable Boot Modes
• Supports booting from BootROM
• Supports booting from SPI NOR Flash
• Supports booting from SPI NAND Flash
• Supports booting from eMMC
• Supports PCIe slave-chip boot

SDK
• Supports Linux SMP 64bit
• Provides audio codec libraries for multiple protocols
• Provides high-performance PC decoding libraries for H.265/H.264

Chip Physical Specifications
• Power consumption
− Typical scenario (16-channel 1080p@15fps encoding + 16-channel 1080p@15fps decoding + deep learning intelligent algorithm) power consumption: 4.6W
− Supports multi-level power control
• Operating voltage
− Core voltage 0.9V
− CPU voltage 1.0V
− IO voltage 1.8V/3.3V
− DDR4 interface voltage 1.2V
− DDR3 interface voltage 1.5V
• Package
− RoHS, EHS-TFBGA
− Pin pitch: 0.8mm
− Package size: 22.4mm x 31.2mm
− Operating temperature: 0°C ~ 70°C

3. Interface Circuits

1. 12V to 5V circuit interface (12V power supply)

2. Network + USB interface circuit

3. DEBUG serial port

4. Reset interface circuit

4. FAQ