HiSiliconHI3519DV500Decoder Board
Project: Board Introduction | page_id: 1309
Product Introduction
Board Size: 108*60mm
Chip Specifications
Description
Hi3519DV500 is an ultra HD smart SoC launched for the vision industry. This chip supports up to 4-channel sensor input, supports ISP image processing capability up to 4K@30fps, supports 2F WDR, multi-level noise reduction, 6-axis anti-shake, panoramic stitching, multi-spectral fusion and other traditional image enhancement and processing algorithms, and supports real-time noise reduction of input images through AI algorithms, providing users with excellent image processing capability.
Features
Processor Core
• Dual-core ARM Cortex A55@1000MHz • 32KB I-Cache, 32KB D-Cache, 256KB L3 cache • Supports NEON acceleration, integrated FPU processing unit • Supports TrustZone
System-Level Acceleration Module
• Integrated hardened standard CRC32/CRC16/CRC8 polynomial operation unit • Integrated hardened high-speed direct data transfer module (DMA)
Intelligent Video Analysis
• Neural network: supports complete API and tool chain, easy for customer development • Upgraded IVE operator, supports feature point detection, perimeter, optical flow and various computer morphology operators • Upgraded DPU algorithm to implement binocular depth map acceleration unit, max resolution 2048 x 2048, max disparity 224, processing performance 720p@30fps
Video Codec
• Supports H.264 BP/MP/HP Level 5.1 • Supports H.265 Main Profile Level 5.1 • H.264/H.265 codec max resolution 6144x 6144 • Supports I/P frames • H.264/H.265 multi-stream codec typical performance as follows: −3840 x 2160@30fps(encoding)+1920 x 1080@30fps(encoding)+720 x 480@30fps(encoding) −3840 x 2160@30fps(encoding)+720 x 480@30fps(encoding)+1920 x 1080@30fps(decoding) −3840 x 2160@30fps(decoding) • Supports pre-encoding OSD overlay for 8 regions • Supports CBR/VBR/AVBR/FIXQP/QPMAP and other rate control modes • Max output bitrate 80Mbps • Supports 8 regions of interest (ROI) encoding • Supports video front-end mosaic overlay encoding • Supports digital watermark • Supports PVC perceptual encoding to reduce bitrate • Supports JPEG Baseline codec • JPEG codec max resolution 16384 x 16384 • JPEG max performance −Encoding: 3840 x 2160@60fps(YUV420) −Decoding: 3840 x 2160@30fps(YUV420)
ISP
• Supports simultaneous processing of multiple sensors • Supports 3A (AE/AWB/AF) function, 3A parameters adjustable by users • Supports fixed pattern noise (FPN) removal • Supports bad pixel correction and lens shading correction • Supports two-frame WDR and Advanced Local Tone Mapping, supports strong light suppression and backlight compensation • Supports multi-level 3D denoising • Supports image edge enhancement • Supports defog • Supports dynamic contrast enhancement • Supports 3D-LUT color adjustment • Supports new generation lens distortion correction • Supports fisheye and arbitrary shape geometric correction • Supports 6-DoF digital image stabilization • Supports gyroscope image stabilization and Rolling-Shutter correction • Supports image Mirror, Flip, 90 degree / 270 degree rotation • Supports using neural network for real-time DRC, BNR, 3DNR or DM processing of images • Supports dual-light fusion of black-white and color images • Provides PC-side ISP tuning tools
Video and Graphics Processing
• Supports graphics and image 1/15.5～16x scaling function • Supports horizontal panoramic stitching −Input 2 channels 2560×1440@30fps, max output 5120x1440@30fps or 2560x2880@30fps −Input 4 channels 1920x1080@30fps, max output 6144x1080@30fps or 1920x4320@30fps • Supports video layer and graphics layer overlay • Supports color space conversion
Video Input Interface
• Supports 8-Lane image sensor serial input, supports MIPI/LVDS/Sub-LVDS/HiSPi multiple interfaces • Supports 2x4-Lane or 4x2-Lane and other combinations, supports up to 4-channel sensor input • Supports 8/10/12/14 Bit RGB Bayer DC timing video input, clock frequency up to 148.5MHz • Supports BT.601, BT.656, BT.1120 video input interfaces • Supports 1~4 channels YUV input through MIPI virtual channels • Supports mainstream CMOS level thermal imaging sensor access • Supports structured light image module • Supports cw ToF image sensor
Video Output Interface
• Supports one BT.1120 or BT.656 interface output, of which BT.1120 max performance 1920x1080@60fps • Supports 6/8bit serial or 16/18/24bit RGB parallel output, max frequency 74.25MHz • Supports 4-Lane MIPI DSI/CSI interface output, up to 1.8Gbps/lane, performance 3840 x 2160@30fps • Supports Gamma correction and horizontal sharpen
Audio Interface and Processing
• Built-in Audio codec, supports 16bit dual-channel differential voice input and dual-channel single-ended voice output • Supports 1 I2S interface, compatible with multi-channel time division multiplexing transmission mode (TDM) • Supports 8-channel digital MIC array input • Supports multi-protocol voice codec • Supports audio 3A (AEC/ANR/ALC) processing
Security Isolation and Engine
• Supports secure boot • Supports TrustZone-based REE/TEE hardware isolation solution • Supports neural network model and data protection • Hardware implementation of AES128/256 symmetric encryption algorithm • Hardware implementation of RSA3072/4096 signature verification algorithm • Hardware implementation of ECC256/384/512 elliptic curve algorithm • Hardware implementation of SHA256/384/512, HMAC_SHA256/384/512 algorithms • Hardware implementation of SM2/3/4 national cryptographic algorithms • Hardware implementation of true random number generator • Provides 28Kbit OTP storage space for customers
Network Interface
• 1 Gigabit Ethernet interface −Supports RGMII, RMII interface modes −Supports TSO, UFO, COE and other acceleration units
Peripheral Interfaces
• 2 SDIO3.0 interfaces −SDIO0 supports SDXC card, max capacity 2TB −SDIO1 supports connecting WiFi module • 1 USB3.0/USB2.0 interface −USB Host/Device switchable • Supports power-on reset (POR) and external input reset • Integrated independent power supply RTC • Integrated simplified power-up/down control logic to realize chip standby wakeup • Integrated 4-channel LSADC • Integrated RGB small screen dedicated three-wire control interface • Multiple UART, I²C, SPI, PWM, GPIO interfaces
External Memory Interface
• DDR4/LPDDR4/LPDDR4x interface −Supports 2 x 16bit DDR4 −Supports 1 x 32bit LPDDR4/LPDDR4x −DDR4 max rate 2666Mbps −LPDDR4/LPDDR4x max rate 2666Mbps −Max capacity 4GB • SPI Nor/SPI Nand Flash interface −Supports 1, 2, 4-wire modes −SPI Nor Flash supports 3Byte, 4Byte address modes • eMMC5.1 interface, max capacity 2TB • Can choose to boot from eMMC, SPI Nor/SPI Nand Flash
SDK
Supports Linux5.10 SDK package
Chip Physical Specifications
• Power consumption −2.5W typical power consumption (4K30 encoding + 2TOPS) • Operating voltage −Core voltage 0.9V −IO voltage 1.8/3.3V −DDR4/LPDDR4/LPDDR4x interface voltages are 1.2/1.1/0.6V respectively • Package −RoHS, FCCSP 15mm x 15mm package −Pin pitch: 0.65mm
Interface Circuits
Power
Network Port
Light Board Power Supply
Light Board Control Port
IR-CUT
MIC Interface
Range lens
JTAG Interface
I2C Interface
VBAT Interface
HDMI Loop-out
TYPE-C_USB Interface
Debug Interface
SD Card Interface
