HiSilicon HI3519DV500 Board: 3× HDMI + 1× DVI Loop-Through, SDI_UVC Dual-Lens Input

Project: Board Introduction | page_id: 1652

I. Product Images

Board Size: 165*115mm

II. Chip Specifications

Description

Hi3519DV500 is an ultra-high-definition intelligent SoC launched for the vision industry. This chip supports up to 4-channel sensor input, supports ISP image processing capability up to 4K@30fps, supports 2F WDR, multi-level noise reduction, six-axis anti-shake, panoramic stitching, multi-spectral fusion and other traditional image enhancement and processing algorithms, and supports real-time noise reduction and other processing of input images through AI algorithms, providing users with excellent image processing capabilities.
Features

Processor Core

• Dual-core ARM Cortex A55@1000MHz • 32KB I-Cache, 32KB D-Cache, 256KB L3 cache • Supports NEON acceleration, integrated FPU processing unit • Supports TrustZone
System-Level Acceleration Module
• Integrated hardened standard CRC32/CRC16/CRC8 polynomial operation unit • Integrated hardened high-speed direct data transfer module (DMA)

Intelligent Video Analysis

• Neural network: supports a complete API and tool chain, easy for customer development • Upgraded IVE operators, supporting feature point detection, perimeter, optical flow and various computer morphology operators • Upgraded DPU algorithm to implement a binocular depth map acceleration unit, with a maximum resolution of 2048 x 2048, a maximum parallax of 224, and a processing performance of 720p@30fps

Video Codec

• Supports H.264 BP/MP/HP Level 5.1 • Supports H.265 Main Profile Level 5.1 • Maximum H.264/H.265 encoding and decoding resolution is 6144 x 6144 • Supports I/P frames • Typical performance of H.264/H.265 multi-stream encoding and decoding is as follows: −3840 x 2160@30fps (encoding) + 1920 x 1080@30fps (encoding) + 720 x 480@30fps (encoding) −3840 x 2160@30fps (encoding) + 720 x 480@30fps (encoding) + 1920 x 1080@30fps (decoding) −3840 x 2160@30fps (decoding) • Supports OSD overlay for 8 areas before encoding • Supports CBR/VBR/AVBR/FIXQP/QPMAP and other bitrate control modes • Maximum output bitrate 80Mbps • Supports encoding of 8 regions of interest (ROI) • Supports video front-end overlay mosaic encoding • Supports digital watermark • Supports PVC perceptual encoding to reduce the bitrate • Supports JPEG Baseline encoding and decoding • Maximum JPEG encoding and decoding resolution 16384 x 16384 • Maximum JPEG performance −Encoding: 3840 x 2160@60fps (YUV420) −Decoding: 3840 x 2160@30fps (YUV420)

ISP

• Supports simultaneous processing of multiple sensors • Supports 3A (AE/AWB/AF) functions, 3A parameters are user adjustable • Supports fixed pattern noise removal (FPN) • Supports bad point correction and lens shading correction • Supports two-frame WDR and Advanced Local Tone Mapping, supports highlight suppression and backlight compensation • Supports multi-level 3D denoising • Supports image edge enhancement • Supports defog • Supports dynamic contrast enhancement • Supports 3D-LUT color adjustment • Supports new generation lens distortion correction • Supports fisheye and other arbitrary shape geometric correction • Supports 6-DoF digital image stabilization • Supports gyroscope stabilization and Rolling-Shutter correction • Supports image mirror, flip, 90°/270° rotation • Supports real-time DRC, BNR, 3DNR or DM processing of images using neural networks • Supports dual-light fusion of black-and-white and color images • Provides a PC-side ISP tuning tool

Video and Graphics Processing

• Supports graphics and image scaling from 1/15.5 to 16x • Supports horizontal panoramic stitching −Input 2 channels of 2560×1440@30fps, maximum output 5120x1440@30fps or 2560x2880@30fps −Input 4 channels of 1920x1080@30fps, maximum output 6144x1080@30fps or 1920x4320@30fps • Supports video layer and graphics layer overlay • Supports color space conversion

Video Input Interface

• Supports 8-Lane image sensor serial input, supports MIPI/LVDS/Sub-LVDS/HiSPi interfaces • Supports 2x4-Lane or 4x2-Lane and other combinations, up to 4-channel sensor input • Supports 8/10/12/14 Bit RGB Bayer DC timing video input, with a clock frequency up to 148.5MHz • Supports BT.601, BT.656, BT.1120 video input interfaces • Supports 1~4 channels of YUV input through MIPI virtual channels • Supports mainstream CMOS level thermal imaging sensor access • Supports structured light image modules • Supports cw ToF image sensors

Video Output Interface

• Supports one BT.1120 or BT.656 interface output, of which BT.1120 has a maximum performance of 1920x1080@60fps • Supports 6/8bit serial or 16/18/24bit RGB parallel output, with a maximum frequency of 74.25MHz • Supports 4-Lane MIPI DSI/CSI interface output, up to 1.8Gbps/lane, with a performance of 3840 x 2160@30fps • Supports Gamma correction and horizontal sharpen

Audio Interface and Processing

• Built-in audio codec, supports 16bit dual-channel differential voice input and dual-channel single-ended voice output • Supports 1 I2S interface, compatible with multi-channel time division multiplexing (TDM) • Supports 8-channel digital MIC array input • Supports multi-protocol voice codec • Supports audio 3A (AEC/ANR/ALC) processing
Security Isolation and Engine
• Supports secure boot • Supports TrustZone-based REE/TEE hardware isolation • Supports neural network model and data protection • Hardware implementation of the AES128/256 symmetric encryption algorithm • Hardware implementation of the RSA3072/4096 signature verification algorithm • Hardware implementation of the ECC256/384/512 elliptic curve algorithm • Hardware implementation of SHA256/384/512 and HMAC_SHA256/384/512 algorithms • Hardware implementation of the SM2/3/4 national cryptographic algorithms • Hardware implementation of a true random number generator • Provides 28Kbit OTP storage space for customers

Network Interface

• 1 Gigabit Ethernet interface −Supports RGMII and RMII interface modes −Supports TSO, UFO, COE and other acceleration units
Peripheral Interfaces
• 2 SDIO3.0 interfaces −SDIO0 supports SDXC cards, with a maximum capacity of 2TB −SDIO1 supports connecting to WiFi modules • 1 USB3.0/USB2.0 interface −USB Host/Device switchable • Supports power-on reset (POR) and external input reset • Integrated independently powered RTC • Integrated simplified power-on/power-off control logic to realize chip standby wake-up • Integrated 4-channel LSADC • Integrated dedicated three-wire control interface for small RGB screens • Multiple UART, I²C, SPI, PWM, GPIO interfaces

External Memory Interface

• DDR4/LPDDR4/LPDDR4x interface −Supports 2 x 16bit DDR4 −Supports 1 x 32bit LPDDR4/LPDDR4x −DDR4 maximum rate 2666Mbps −LPDDR4/LPDDR4x maximum rate 2666Mbps −Maximum capacity 4GB • SPI Nor/SPI Nand Flash interface −Supports 1, 2, 4-wire modes −SPI Nor Flash supports 3Byte and 4Byte address modes • eMMC5.1 interface, maximum capacity 2TB • Boot from eMMC, SPI Nor/SPI Nand Flash can be selected
Boot SDK supports the Linux 5.10 SDK package

Chip Physical Specifications

• Power consumption −2.5W typical power consumption (encoding 4K30 + 2TOPS) • Operating voltage −Core voltage 0.9V −IO voltage 1.8/3.3V −DDR4/LPDDR4/LPDDR4x interface voltages are 1.2/1.1/0.6V respectively • Package form −RoHS, FCCSP 15mm x 15mm package −Pin pitch: 0.65mm

III. Interface Circuits

Power Supply

RJ45

USB_Drive Port

HDMI_OUT3

HDMI_OUT2

DVI_Output

USB_UVC-2

USB_UVC-1

HDMI_OUT1

Battery_Port

MCU Burning-Port

Reserved Serial Port

SDI_IN

SDI_Serial

Debug

12V Power

USB_Port

Button panel

Serial Screen

IV. FAQ