HiSiliconhi3516ev200+GC2053Development Board

Project: Board Introduction | page_id: 1059

1. Product Images

Board dimensions: 38*38mm

2. CPU Parameters

Description

As a new generation of industry-specific HD IP camera SOC, Hi3516EV200 integrates a new generation ISP and the industry's latest H265 video compression encoder. It also adopts an advanced low-power process and low-power architecture design, making Hi3516EV200 lead the industry in low bitrate, high image quality and low power consumption. It integrates POR, RTC and Audio Codec, greatly reducing the ebom cost for customers. And with an interface design similar to that of Shanghai HiSilicon DVR/NVR chips, it can easily support customer product development and mass production.

• Integrated new generation ISP

• The latest H265 video compression encoder, low bitrate, high image quality

• Integrated POR, RTC, Audio Codec

Features

Processor Core
• ARM Cortex A7@ 900MHz，32KB I-Cache， 32KB D-Cache /128KB L2 cache
• Supports Neon acceleration, integrated FPU processing unit

Video Encoding
• H.264 BP/MP/HP，supports I/P frames
• H.265 Main Profile，supports I/P frames
• MJPEG/JPEG Baseline encoding

Video Encoding Processing Performance
• H.264/H.265 encoding supports a maximum resolution of 2304x1296, with a maximum width of 2304
• H.264/H.265 multi-stream real-time encoding capability:
− 2048x1536@20fps+720x576@20fps
− 2304x1296@20fps+720x576@20fps
− 1920x1080@30fps+720x576@30fps
• Supports JPEG snapshot 3M (2304x1296) @5fps
• Supports six bitrate control modes: CBR/VBR/FIXQP/AVBR/QPMAP/CVBR
• Supports intelligent encoding mode
• Output bitrate up to 60Mbps
• Supports encoding of 8 regions of interest (ROI)

Intelligent Video Analysis
• Integrated IVE intelligent analysis acceleration engine
• Supports intelligent motion detection, perimeter protection, video diagnosis and other intelligent analysis applications

Video and Graphics Processing
• Supports 3D denoising, image enhancement, dynamic contrast enhancement processing functions
• Supports anti-flicker processing for video and graphics output
• Supports video and graphics 1/15～16x scaling
• Supports video and graphics overlay
• Supports image rotation by 90, 180, 270 degrees
• Supports image Mirror and Flip functions
• Pre-encoding OSD overlay for 8 regions

ISP
• Supports 4x4 Pattern RGB-IR sensor
• 3A (AE/AWB/AF), supports third-party 3A algorithms
• Fixed pattern noise elimination, defective pixel correction
• Lens shading correction, lens distortion correction, purple fringing correction
• Direction-adaptive demosaic
• Gamma correction, dynamic contrast enhancement, color management and enhancement
• Region-adaptive defog
• Multi-level noise reduction (BayerNR, 3DNR) and sharpening enhancement
• Local Tone mapping
• Sensor Built-in WDR
• 2F-WDR frame mode
• Digital image stabilization
• Supports intelligent ISP adjustment, provides PC-side ISP tuning tools

Audio Codec
• Multi-protocol voice codec implemented by software
• Protocol support: G.711、G.726、ADPCM
• Supports audio 3A (AEC, ANR, AGC) functions

Security Engine
• Hardware implementation of AES/RSA encryption and decryption algorithms
• Hardware implementation of HASH (SHA1/SHA256/HMAC_SHA1/HMAC_SHA256)
• Internal 32Kbit one-time programmable space and random number generator

Video Interface
• Input
− Supports 8/10/12bit RGB Bayer DC timing video input
− Supports MIPI、LVDS/Sub-LVDS、HiSPi interfaces
− Supports connection with mainstream HD CMOS sensors from SONY、ON、OmniVision、Panasonic, etc.
− Compatible with the electrical characteristics of various sensor parallel/differential interfaces
− Provides programmable sensor clock output
− Supports a maximum input resolution of 2304x1296
• Output
− Supports 6/8bit LCD output
− Supports BT656/BT1120 output

Audio Interface
• Integrated Audio codec, supports 16bit voice input and output
• Supports mono mic/line in input
• Supports mono line out output
• Supports I2S interface, supports connection to an external Audio codec

Peripheral Interfaces
• Supports POR
• Integrated high-precision RTC
• Integrated 2-channel LSADC
• 3 UART interfaces
• Supports I2C、SPI、GPIO and other interfaces
• 4 PWM interfaces
• 1 SDIO2.0 + 1 SD card 2.0
• 1 USB 2.0 HOST/Device interface
• Integrated FE PHY; supports TSO network acceleration

External Memory Interface
• SDRAM interface
− Built-in 512Mb DDR2
• SPI NOR Flash interface
− Supports 1、2、4-wire modes
− Maximum capacity 256MB
• SPI NAND Flash interface
− Supports 1、2、4-wire modes
− Maximum capacity 1GB
• eMMC4.5 interface
− 4bit data width

Boot
• Can choose to boot from SPI NOR Flash, SPI NAND Flash or eMMC
• Supports secure boot

SDK
• Provides SDK package based on HUAWEI LiteOS/Linux-4.9
• Provides high-performance PC decoding library for H.264
• Provides high-performance PC, Android, iOS decoding for H.265

Chip Physical Specifications
• Power Consumption
− 1080P30/3M20 scenario, 700mW typical power consumption
• Operating Voltage
− Core voltage 0.9V − IO voltage 3.3V (+/-10%)
− SDRAM interface voltage 1.8V
• Package
− 9mm x 9mm，88pin 0.35mm pin pitch，QFN package

3. Hardware Interface Diagram

(1) power

(2)IRCUT

(3) Audio input, audio output, USB interface

(4) uart debug

（5）tf card

4. FAQ