HiSilicon3519DV5 DSPModule

Project: Board Card Introduction | page_id: 1707

Product Images

HI3519DV5 IPC

OS08A20-XSW3519DV5 Sensor

CPU Specifications

HI3519DV500

Description

Hi3519DV500 is an ultra HD smart SoC launched for the vision industry. The chip supports up to four sensor inputs, supports ISP image processing capability up to 4K@30fps, supports 2F WDR, multi-level noise reduction, six-axis anti-shake, panoramic stitching, multi-spectral fusion and a variety of other traditional image enhancement and processing algorithms, and supports real-time noise reduction and other processing of input images through AI algorithms, providing users with excellent image processing capabilities.
Features

Processor Core
• Dual-core ARM Cortex A55@1000MHz• 32KB I-Cache, 32KB D-Cache, 256KB L3 cache• Supports NEON acceleration, integrated FPU processing unit• Supports TrustZone

System-Level Acceleration Module
• Integrated hardened standard CRC32/CRC16/CRC8 polynomial operation unit• Integrated hardened high-speed direct data transfer module (DMA)

Intelligent Video Analysis
• Neural network Supports a complete API and tool chain, easy for customer development• Upgraded IVE operators, supporting feature point detection, perimeter, optical flow and various computer morphology operators• Upgraded DPU algorithm to implement a binocular depth map acceleration unit, max resolution 2048 x 2048, max disparity 224, processing performance 720p@30fps

Video Codec
• Supports H.264 BP/MP/HP Level 5.1• Supports H.265 Main Profile Level 5.1• H.264/H.265 codec max resolution is 6144x 6144• Supports I/P frames• Typical H.264/H.265 multi-stream codec performance is as follows: −3840 x 2160@30fps (encoding) + 1920 x 1080@30fps (encoding) + 720 x 480@30fps (encoding) −3840 x 2160@30fps (encoding) + 720 x 480@30fps (encoding) + 1920 x 1080@30fps (decoding) −3840 x 2160@30fps (decoding)• Supports pre-encoding OSD overlay for 8 regions• Supports multiple rate control modes such as CBR/VBR/AVBR/FIXQP/QPMAP• Maximum output bitrate 80Mbps• Supports encoding of 8 regions of interest (ROI)• Supports video front-end overlay mosaic encoding• Supports digital watermark• Supports PVC perceptual encoding to reduce the bitstream• Supports JPEG Baseline codec• JPEG codec max resolution 16384 x 16384• Maximum JPEG performance −Encoding: 3840 x 2160@60fps (YUV420) −Decoding: 3840 x 2160@30fps (YUV420)

ISP
• Supports simultaneous processing of multiple sensors• Supports 3A (AE/AWB/AF) functions, 3A parameters are adjustable by the user• Supports fixed pattern noise (FPN) removal• Supports bad point correction and lens shading correction• Supports two-frame WDR and Advanced Local Tone Mapping, supports strong light suppression and backlight compensation• Supports multi-level 3D noise reduction• Supports image edge enhancement• Supports defogging• Supports dynamic contrast enhancement• Supports 3D-LUT color adjustment• Supports a new generation of lens distortion correction• Supports geometric correction of arbitrary shapes such as fisheye• Supports 6-DoF digital image stabilization• Supports gyroscope anti-shake and Rolling-Shutter correction• Supports image Mirror, Flip, 90-degree/270-degree rotation• Supports real-time DRC, BNR, 3DNR or DM processing of images using neural networks• Supports dual-light fusion of black-and-white and color images• Provides a PC-side ISP tuning tool

Video and Graphics Processing
• Supports graphics and image 1/15.5～16x scaling • Supports horizontal panoramic stitching −Input 2 channels of 2560×1440@30fps, max output 5120x1440@30fps or 2560x2880@30fps −Input 4 channels of 1920x1080@30fps, max output 6144x1080@30fps or 1920x4320@30fps • Supports video layer and graphics layer overlay • Supports color space conversion

Video Input Interface
• Supports 8-Lane image sensor serial input, supports MIPI/LVDS/Sub-LVDS/HiSPi interfaces• Supports 2x4-Lane or 4x2-Lane and other combinations, supports up to 4 sensor inputs• Supports 8/10/12/14 Bit RGB Bayer DC timing video input, clock frequency up to 148.5MHz• Supports BT.601, BT.656, BT.1120 video input interfaces• Supports input of 1~4 channels of YUV through MIPI virtual channels• Supports access to mainstream CMOS-level thermal imaging sensors• Supports structured light image modules• Supports cw ToF image sensors

Video Output Interface
• Supports one BT.1120 or BT.656 interface output, of which BT.1120 has a maximum performance of 1920x1080@60fps• Supports 6/8bit serial or 16/18/24bit RGB parallel output, max frequency 74.25MHz• Supports 4-Lane Mipi DSI/CSI interface output, up to 1.8Gbps/lane, performance 3840 x 2160@30fps• Supports Gamma correction and horizontal sharpen

Audio Interface and Processing
• Built-in Audio codec, supports 16bit dual-channel differential voice input and dual-channel single-ended voice output• Supports 1 I2S interface, compatible with multi-channel time division multiplexing transmission mode (TDM)• Supports 8-channel digital MIC array input• Supports multi-protocol voice codec• Supports audio 3A (AEC/ANR/ALC) processing

Security Isolation and Engine
• Supports secure boot• Supports REE/TEE hardware isolation solution based on TrustZone• Supports neural network model and data protection• Hardware implementation of AES128/256 symmetric encryption algorithm• Hardware implementation of RSA3072/4096 signature verification algorithm• Hardware implementation of ECC256/384/512 elliptic curve algorithm• Hardware implementation of SHA256/384/512, HMAC_SHA256/384/512 algorithms• Hardware implementation of SM2/3/4 national cryptography algorithms• Hardware implementation of a true random number generator• Provides 28Kbit OTP storage space for customer use

Network Interface
• 1 Gigabit Ethernet interface −Supports RGMII and RMII interface modes −Supports acceleration units such as TSO, UFO and COE

Peripheral Interfaces
• 2 SDIO3.0 interfaces −SDIO0 supports SDXC cards, max capacity 2TB −SDIO1 supports connecting to a WiFi module • 1 USB3.0/USB2.0 interface −USB Host/Device switchable • Supports power-on reset (POR) and external input reset • Integrates an independently powered RTC • Integrates simplified power-up/power-down control logic to implement chip standby wake-up • Integrates 4-channel LSADC • Integrates a dedicated three-wire control interface for small RGB screens • Multiple UART, I²C, SPI, PWM and GPIO interfaces

External Memory Interface
• DDR4/LPDDR4/LPDDR4x interface −Supports 2 x 16bit DDR4 −Supports 1 x 32bit LPDDR4/LPDDR4x −DDR4 max rate 2666Mbps −LPDDR4/LPDDR4x max rate 2666Mbps −Max capacity 4GB • SPI Nor/SPI Nand Flash interface −Supports 1, 2 and 4-wire modes −SPI Nor Flash supports 3Byte and 4Byte address modes • eMMC5.1 interface, max capacity 2TB • Boot from eMMC, SPI Nor/SPI Nand Flash can be selected

SDK
Supports the Linux5.10 SDK package

Chip Physical Specifications
• Power consumption −2.5W typical power consumption (encoding 4K30 + 2TOPS) • Operating voltage −Core voltage is 0.9V −IO voltage is 1.8/3.3V −DDR4/LPDDR4/LPDDR4x interface voltages are 1.2/1.1/0.6V respectively • Package form −RoHS, FCCSP 15mm x 15mm package −Pin pitch: 0.65mm