HiSiliconHI3516DV300Module

Project: Board Introduction | page_id: 1324

Product Introduction

Board Size: 38*38mm

Chip Specifications

describe
As a new generation of industry-specific Smart HD IP camera SOC, Hi3516DV300 integrates a new generation ISP, the latest H.265 video compression encoder in the industry, and a high-performance NNIE engine, making Hi3516DV300 lead the industry in low bitrate, high image quality, intelligent processing and analysis, low power consumption, and other aspects. Integrating POR, RTC, Audio codec, and standby wake-up circuit greatly reduces the cost of Ebom for customers. And the interface design similar to the HiSilicon DVR/NVR chip can easily support customer product development and mass production.
• Integrate new generation ISP
The latest H.265 video compression encoder
• Integrated high-performance NNIE engine, 1Tops computing power
characteristic
Processor core
Dual core ARM Cortex-A7 @ 900MHz, 32KB I-Cache, 32KB D-Cache, 256KB L2 Cache
• Supports NEON acceleration and integrates FPU processing unit
Video Encoding and Decoding
• H.264 BP/MP/HP
• H.265 Main Profile
• Supports I/P frames and Smart P references
MJPEG/JPEG Baseline Encoding
Video encoding processing performance
H.264/H.265 codec has a maximum width of 3072 and a maximum resolution of 3072x1728, and only supports decoding its own encoded stream
H.264/H.265 multi stream real-time encoding (decoding) capability:
− 2688x1536@30fps Encoding+ 720x480@30fps code

360x240@30fps code
− 2688x1944@20fps Encoding+ 720x480@20fps code
360x240@20fps code
− 1920x1080@30fps Encoding+ 720x480@30fps code
1920x1080@30fps decode
JPEG encoding and decoding capabilities:
− 16M(4608x3456) @10fps
• Supports five rate control modes: CBR/VBR/FIXQP/AVBR/QPMAP
• Output bitrate up to 50Mbps
• Supports encoding of 8 regions of interest (ROI)
Intelligent video analysis
Integrated neural network acceleration engine, with a processing performance of 1.0 Tops
Integrated intelligent computing acceleration engine (including tracking and face correction)
Video and Graphics Processing
3D denoising, image enhancement, and dynamic contrast enhancement processing functions
Anti flicker processing for video and graphic output
Video and graphics 1/15-16x zoom function
Video graphic overlay
Rotate the image 90, 180, 270 degrees
Image Mirror and Flip functions
Pre coding OSD overlay for 8 regions
ISP
• 3A（AE/AWB/AF）， Support third-party 3A algorithm
Fixed mode noise elimination and bad pixel correction
• Lens shadow correction, lens distortion correction, purple edge correction
• Direction adaptive demo
Gamma correction, dynamic contrast enhancement, color management, and enhancement
• Region adaptive defogging
Multi level noise reduction (Bayer NR, 3DNR), detail enhancement, and sharpening enhancement
• Local Tone mapping
Sensor built-in WDR and 2F WDR (line base/frame base/DCG)
• Supports 6-DOF stabilization (based on video or gyroscope information)
• Provide PC ISP tuning tools
Audio codec
• Implement multi protocol speech encoding and decoding (G.711, G.726, ADPCM) through software
• Supports audio 3A (AEC, ANR, AGC) function
secure
• Support secure boot
Hardware implementation of memory isolation
Hardware implementation of AES/DES/3DES/RSA multiple encryption and decryption algorithms
Hardware implementation of HASH (SHA1/SHA256/HMAC_SHA/HMAC_SHA256)
• Integrated hardware random number generator
• Integrated 8K bit OTP storage space
video interface
• Input
Supports two inputs
The first input supports a maximum width of 2688 and a maximum resolution of 2688x1944
The second channel supports a maximum input width of 2048 and a maximum resolution of 2048 x 1536
Supports 8/10/12/14 bit RGB Bayer DC timing video input
Supports BT.601, BT.656, BT.1120 video input interfaces
Supports MIPI, LVDS/Sub LVDS, HiSPi interfaces
Support docking with mainstream high-definition CMOS sensors such as SONY, ON, OmniVision, Panasonic, etc
Compatible with multiple sensors, parallel/differential interface electrical characteristics
Provide programmable sensor clock output
• Output
Supports 1 BT.656/BT.1120 video output interface
Supports 6/8-bit serial, 16/18/24bit RGB parallel LCD output
Supports 4Lane Mipi DSI interface output
Supports HDMI 1.4 output (maximum resolution 1080p60)
Audio Interface
Integrated Audio codec, supporting 16 bit voice input and output
• Supports monaural mic differential input to reduce background noise
• Supports single ended dual channel input
• Supports I2S interface and interfaces with external audio codecs
Peripheral interface
• Integrated POR
• Integrated high-precision RTC
• Integrated 2-channel LSADC
Several I2C, SPI, UART interfaces
3 PWM interfaces
2 SDIO3.0 interfaces, supporting 3.3/1.8V voltage levels
One of them supports SD3.0 cards
• 1 USB 2.0 Host/Device interface
• Support RMII mode; Support TSO network acceleration; Supports 10/100Mbps full duplex or half duplex mode, providing PHY clock output
External memory interface
SDRAM interface
− 32bit DDR3(L)/DDR4， Maximum capacity supports 16Gbit
Maximum speed of 1800Mbps
SPI Nor Flash interface
Supports 1, 2, and 4-wire modes
Maximum capacity support 256MB
SPI Nand Flash interface
Maximum ECC error correction capability of 24bit/1KB
Maximum capacity supports 1GB
EMMC4.5 interface
-4-bit data bit width
start-up
• Can be started from SPI Nor Flash, SPI Nand Flash, or eMMC
SDK
• Provide Linux-4.9 SDK package
Provide a high-performance PC decoding library for H.264
• Provide high-performance H.265 decoding libraries for PC, Android, and iOS
Chip physical specifications
• Power consumption
4M (2688 x 1536) P30, TBD typical power consumption
• Working voltage
The core voltage is 0.9V
IO voltage is 3.3V (+/-10%)
DDR3 (L)/4 SDRAM interface voltage is 1.5 (1.35)/1.2V
• Encapsulation
14mm x 14mm, 367pin 0.65 pin spacing, TFBGA RoHS

Interface Circuits

Power

Network Port / IRCUT Hard Photosensitive Interface

SD Card / 3V3 / USB / GPIO

UART0 Serial Port / UART1 / GPIO Port

Audio Left/Right Channel / Speaker Interface

FAQ