HiSiliconHI3516CV610 SDIEncoder Board

Project: Board Introduction | page_id: 1660

I. Product Images

Board Size: 76*50mm

II. Chip Specifications

Main Control Model: HI3516CV610

Features

Processor Core
• Supports ARM Cortex-A7 MP2 • Clock rate 950MHz • Supports 32KB I-Cache, 32KB D-Cache, 128KB L2 cache • Supports Neon and FPU

Intelligent Engine
• Neural network processor NPU −Supports 1Tops computing performance −Supports hundreds of mainstream algorithms in the industry, supporting rapid commercialization by customers −Supports Transformer feature acceleration, with a built-in dedicated multimodal large model −Tools support efficient model production and evolution −Built-in algorithms such as face/human shape/vehicle shape detection, package detection and pet detection • IVE2.5 upgraded operators, supporting motion detection, perimeter protection, tracking, perspective transformation, video diagnosis and various intelligent analysis applications

AI ISP Processing
• Supports basic ISP functions −Supports static and dynamic bad point correction −Supports 3A (AE/AWB/AF) functions, parameters are user adjustable −Supports lens shading correction • Supports high dynamic range −Supports two-frame WDR fusion −Supports Advanced Local Tone Mapping −Supports highlight suppression and backlight compensation • Sharpness and noise reduction −Supports fixed pattern noise removal (FPN) −Motion area effect enhancement algorithm −Supports temporal and spatial denoising −Supports multi-level motion detection −Supports regional enhancement −Supports color noise removal 2.0 • Color management and contrast enhancement −Supports purple fringing removal 2.0 −Supports key color enhancement −Supports local dynamic contrast enhancement −Supports defog function • PQ Tool 1.2

Video Processing
• Supports image scaling from 1/15.5 to 16x • Supports lens distortion correction • Supports image mirror, flip, 90°/270° rotation

Video Encoding
• New generation public security video codec • Supports H.265 Main Profile Level 5 • Supports H.264 BP/MP/HP Level 5.1, with a maximum encoding resolution of 3840×2160 • Supports I/P frames • Supports smart encoding 2.0 • Supports privacy encoding • Typical multi-stream encoding performance is as follows: −3200×1800@30fps+1280×720@30fps −3840×2160@20fps+1280×720@20fps • Supports CBR/VBR/ABR/AVBR/CVBR/QVBR/FIXQP/QPMAP and other bitrate control modes • Maximum output bitrate 80Mbps • Supports OSD overlay for 8 areas before encoding • Supports encoding of 8 regions of interest (ROI) • Supports JPEG Baseline encoding • Maximum JPEG encoding resolution 16384x16384 • Maximum JPEG encoding performance: −3200×1800@30fps (YUV420) −3840×2160@20fps (YUV420)

Video Input Interface
• Supports MIPI/LVDS/Sub-LVDS/HiSPi interfaces • Supports 2x2-Lane or 4-Lane combinations, up to 2-channel sensor input • Supports 8/10/12 Bit RGB Bayer • Supports 8/10/12 Bit DVP • Supports BT.601, BT.656, BT.1120 video input interfaces

Audio Interface and Processing
• Built-in audio codec, supports 16bit dual-channel differential voice input and single-channel single-ended voice output • Supports 1 I2S interface, compatible with multi-channel time division multiplexing (TDM) • Supports multi-protocol voice codec • Supports 3A (AEC/ANR/ALC) processing 2.0 • Supports wind noise reduction algorithm • Supports cry detection 2.0, improving the wake-up rate

Security Isolation and Engine
• Supports secure boot • Supports secure boot • Supports TrustZone-based REE/TEE hardware isolation • Hardware implementation of AES/RSA/ECC/SHA and other encryption and decryption algorithms • Hardware implementation of the SM2/3/4 national cryptographic algorithms

Peripheral Interfaces
• Integrated FEPHY; supports TSO network acceleration • 2 SDIO2.0 interfaces −Supports SDXC cards −Supports connecting to WiFi modules • 1 USB2.0 Host/Device interface • Supports power-on reset (POR) and external input reset • Integrated independently powered RTC • Integrated multi-channel LSADC • Multiple UART, I²C, SPI, PWM, GPIO interfaces

External Memory Interface
• SDRAM interface Built-in 1Gb DDR3/3L, maximum rate 2133Mbps • SPI Nor Flash interface −Supports 1, 2, 4-wire modes −Maximum capacity 32MB • SPI Nand Flash interface −Supports 1, 2, 4-wire modes −Maximum capacity 512MB • eMMC4.5 interface, 4-bit data width • Boot from eMMC, SPI Nor/SPI Nand Flash can be selected

SDK
• Supports the Linux 5.10 SDK package • Supports OpenHarmony 4.1

Chip Physical Specifications
• Power consumption Typical power consumption: TBD • Operating voltage −Typical core voltage 0.9V −IO voltage 1.8/3.3V −DDR3/3L interface voltages are 1.5V/1.35V respectively • Operating temperature: -20°C~70°C • Package form −RoHS, QFN 9mm x 9mm package −Pin pitch: 0.35mm

III. Interface Circuits

Power Supply

RJ45

SDI0_IN

RTC_BAT

Reserved serial port screen

Debug

TF_Card

RESET

USB2_Port

IV. FAQ