HiSiliconHI3516DV300-QN+sensorModule
Project: Board Introduction | page_id: 1322
Product Introduction
Mainboard Size: 50*40mm
Chip Specifications
Description
As a new generation of industry-specific Smart HD IP camera SOC, Hi3516DV300 integrates a new generation ISP, the industry's latest H.265 video compression encoder, and a high-performance NNIE engine, making Hi3516DV300 lead the industry in low bitrate, high image quality, intelligent processing and analysis, and low power consumption. It integrates POR, RTC, Audio Codec and standby wake-up circuits, greatly reducing the eBOM cost for customers. In addition, with an interface design similar to that of HiSilicon DVR/NVR chips, it can easily support customer product development and mass production.
• Integrates a new generation ISP
• The latest H.265 video compression encoder
• Integrates a high-performance NNIE engine with 1Tops computing power
Features
Processor Core
• Dual-core ARM Cortex-A7@ 900MHz, 32KB I-Cache, 32KB D-Cache, 256KB L2 Cache
• Supports NEON acceleration, integrated FPU processing unit
Video Codec
• H.264 BP/MP/HP
• H.265 Main Profile
• Supports I/P frames, supports Smart P reference
• MJPEG/JPEG Baseline encoding
Video Encoding Processing Performance
• H.264/H.265 codec maximum width 3072, maximum resolution 3072x1728, only supports decoding of its own encoded stream
• H.264/H.265 multi-stream real-time encoding (decoding) capability:
− 2688x1536@30fps encoding + 720x480@30fps encoding
+360x240@30fps encoding
− 2688x1944@20fps encoding + 720x480@20fps encoding
+360x240@20fps encoding
− 1920x1080@30fps encoding + 720x480@30fps encoding
+1920x1080@30fps decoding
• JPEG encoding and decoding capability:
− 16M(4608x3456) @10fps
• Supports CBR/VBR/FIXQP/AVBR/QPMAP five rate control modes
• Max output bitrate 50Mbps
• Supports 8 regions of interest (ROI) encoding
Intelligent Video Analysis
• Integrated neural network acceleration engine, with processing performance up to 1.0Tops
• Integrated intelligent computing acceleration engine (including tracking and face correction)
Video and Graphics Processing
• 3D denoising, image enhancement, dynamic contrast enhancement processing functions
• Anti-flicker processing for video and graphics output
• Video and graphics 1/15～16x scaling function
• Video and graphics overlay
• Image 90, 180, 270 degree rotation
• Image Mirror and Flip functions
• Pre-encoding OSD overlay for 8 regions
ISP
• 3A (AE/AWB/AF), supports third-party 3A algorithms
• Fixed pattern noise removal, bad pixel correction
• Lens shading correction, lens distortion correction, purple fringe correction
• Direction adaptive demosaic
• Gamma correction, dynamic contrast enhancement, color management and enhancement
• Region adaptive defog
• Multi-level noise reduction (BayerNR, 3DNR), detail enhancement and sharpening enhancement
• Local Tone mapping
• Sensor built-in WDR and 2F WDR (line-base/frame-base/DCG)
• Supports 6-DOF image stabilization (based on video or gyroscope information)
• Provides PC-side ISP tuning tools
Audio Codec
• Multi-protocol voice codec implemented by software (G.711, G.726, ADPCM)
• Supports audio 3A (AEC, ANR, AGC) functions
Security
• Supports secure boot
• Hardware implementation of memory isolation
• Hardware implementation of AES/DES/3DES/RSA multiple encryption and decryption algorithms
• Hardware implementation of HASH (SHA1/SHA256/HMAC_SHA/HMAC_SHA256)
• Integrated hardware random number generator
• Integrated 8K bit OTP storage space
Video Interfaces
• Input
− Supports two inputs
The first input supports a maximum width of 2688 and a maximum resolution of 2688x1944
The second input supports a maximum width of 2048 and a maximum resolution of 2048x1536
− Supports 8/10/12/14 bit RGB Bayer DC timing video input
− Supports BT.601, BT.656, BT.1120 video input interfaces
− Supports MIPI, LVDS/Sub-LVDS, HiSPi interfaces
− Supports connection with mainstream HD CMOS sensors from SONY, ON, OmniVision, Panasonic, etc.
− Compatible with various sensor parallel/differential interface electrical characteristics
− Provides programmable sensor clock output
• Output
− Supports 1 BT.656/BT.1120 video output interface
− Supports 6/8bit serial and 16/18/24bit RGB parallel LCD output
− Supports 4Lane MIPI-DSI interface output
− Supports HDMI 1.4 output (max resolution 1080p60)
Audio Interfaces
• Integrated Audio codec, supports 16bit voice input and output
• Supports mono mic differential input to reduce background noise
• Supports single-ended dual-channel input
• Supports I2S interface, supports connecting an external Audio codec
Peripheral Interfaces
• Integrated POR
• Integrated high-precision RTC
• Integrated 2-channel LSADC
• Several I2C, SPI and UART interfaces
• 3 PWM interfaces
• 2 SDIO3.0 interfaces, supporting 3.3/1.8V levels
− One of them supports SD3.0 cards
• 1 USB 2.0 Host/Device interface
• Supports RMII mode; supports TSO network acceleration; supports 10/100Mbps full-duplex or half-duplex mode, and provides PHY clock output
External Memory Interface
• SDRAM interface
− 32bit DDR3(L)/DDR4, maximum capacity supports 16Gbit
− Maximum rate 1800Mbps
• SPI Nor Flash interface
− Supports 1, 2, 4-wire modes
− Maximum capacity supports 256MB
• SPI Nand Flash interface
− Maximum ECC correction capability 24bit/1KB
− Maximum capacity supports 1GB
• eMMC4.5 interface
− 4bit data width
Boot
• Can boot from SPI Nor Flash, SPI Nand Flash or eMMC
SDK
• Provides an SDK package based on Linux-4.9
• Provides a high-performance PC decoding library for H.264
• Provides high-performance PC, Android and iOS decoding libraries for H.265
Chip Physical Specifications
• Power consumption
− 4M(2688 x 1536)P30, TBD typical power consumption
• Operating voltage
− Core voltage 0.9V
− IO voltage 3.3V (+/-10%)
− DDR3(L)/4 SDRAM interface voltage 1.5(1.35)/1.2V
• Package
− 14mm x 14mm, 367pin 0.65 pin pitch, TFBGA RoHS
Interface Circuits
28V Power / 5V_USB / SPIO / IRCUT / Network / sensor MIPI
Debug Serial Port
